1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories (DRAMs) and, more particularly, to a process sequence, cell structure and cell layout that achieves a reduction of DRAM cell size.
2. Background Description
Manufacturing of semiconductor devices is dependent upon the accurate replication of computer aided design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using optical lithography followed by a variety of subtractive (etch), additive (deposition) and material modification (e.g., oxidations, ion implants, etc.) processes. Optical lithography patterning involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern etched into the metallic layer. This illuminated image is reduced in size and patterned into a photosensitive film on the device substrate.
To achieve the required density, 1 Gbit-era DRAMs will require a cell with an area of approximately eight times the lithographic feature size squared. Conventional "8square" folded bit line DRAM cells require a transfer device channel length of one lithographic feature. However, it appears unlikely that the transfer device channel length will scale to one lithographic feature (approximately 0.18.mu.m) in this time frame.